The invention relates to a slicer arrangement including means for determining a slicer level from incoming signal levels and a slicer for slicing the incoming signal levels on the basis of the slicer level thus determined.
Such an arrangement is known from U.S. Pat. No. 5,450,389. The arrangement described therein converts signals from an optical signal reader into signals having well-defined xe2x80x9chighxe2x80x9d and xe2x80x9clowxe2x80x9d levels. For this purpose, the signals from the optical signal reader are sliced with respect to a slicer level by means of a slicer. The slicer level setting is determined from incoming signal levels, particularly in relation to the length of the relevant signal levels.
It is an object of the invention to provide such an arrangement in which the slicer level is determined exclusively by the incoming signal levels and in which the slicer level always is always centered with respect to a xe2x80x9chighxe2x80x9d level of the detected signals and a xe2x80x9clowxe2x80x9d level of the detected signals.
To this end, the arrangement in accordance with the invention is characterized in that the means for determining a slicer level include a first and a second register circuit, which register circuits are connected to an output of a discriminator circuit, which discriminator circuit compares an incoming signal level with a set discrimination level and is adapted to apply an incoming signal level to the first register circuit if the incoming signal level is higher than the set discrimination level and to apply an incoming signal level to the second register circuit if the incoming signal level is lower than the set discrimination level, which first and second register circuit are each adapted to determine a register mean value of at least two different incoming signal levels consecutively applied to the register circuit, and there is a mean-value circuit for supplying a signal having a level which is a mean value of the register mean values determined by the first and second register circuit, which supplied signal represents both the set discrimination level and the slicer level.
Thus, it is achieved that the slicer level is always centered with respect to the high level and the low level of the incoming signal levels applied to the arrangement. Moreover, it is achieved that no d.c. free code is required to guarantee that the slicer level is centered in the eyepattern. Moreover, it is achieved that the arrangement in accordance with the invention discriminates high signal levels from low signal levels on the basis of a provisional discrimination level and by selecting the slicer level so as to be centered with respect to the averaged high and low incoming signal levels. As a result, it is achieved that the arrangement can function correctly without the probability of a high level having to be equal to the probability of a low level, on condition that both levels occur.
A first preferred embodiment of an arrangement in accordance with the invention is characterized in that the first and the second comprise a shift register having a plurality of register positions for consecutively storing incoming signal levels applied by the discriminator circuit, and there is a register mean-value circuit for determining the arithmetic mean of the incoming signal levels stored in the register positions.
The arithmetic mean thus determined for the incoming signal levels stored in the register positions forms a progressive average. Since there is both a shift register for the higher incoming signal levels and a shift register for the lower incoming signal levels, the higher and lower levels being always determined with respect to the discrimination level, there is both an arithmetic mean of the higher signal levels stored in the first shift register and an arithmetic mean for the lower levels stored in the shift register of the second register circuit, which mean values are progressive averages, as a result of which the set discrimination level and the slicer level, as represented by the output signal of the mean-value circuit, are always centered with respect to the arithmetic mean values of the stored higher signal levels and the stored lower signal levels.
A further preferred embodiment of an arrangement in accordance with the invention is characterized in that each of the register circuits performs an operation upon the applied incoming signal levels, which operation is defined in that a new register mean value is determined by multiplying the current register mean value by a factor (1xe2x88x92xcex1), where 0 less than xcex1 less than 1, and adding thereto a new incoming signal level to be added, which last-mentioned incoming signal level has been multiplied by a factor xcex1.
Thus, it is achieved that each register circuit requires only one register position, as a result of which the relevant circuit arrangement can be implemented in hardware form in an economical manner.
A further preferred embodiment of the arrangement in accordance with the invention is characterized in that the register mean value is defined by at least three different incoming signal levels applied consecutively to the register circuit, and the register mean value is the median of the incoming signal levels applied.
Thus, it is achieved that both the higher incoming signal levels and the lower incoming signal levels are filtered by a so-called median filter. Since use is made of the medium the register mean value will be even more reliable than in the preceding preferred embodiment because excessive higher incoming signal levels and excessive lower incoming signal levels are removed by the median filter and have no influence on the process of determining the register mean value.
A further preferred embodiment of an arrangement in accordance with the invention is characterized in that there is a timing circuit for at least one of the register circuits, the timing circuit has an output connected to a control input of the discriminator circuit, the timing circuit is adapted to be started each time that the discriminator circuit supplies an incoming signal level to the respective register circuit, and to supply upon expiry of a predetermined time interval a control signal to the output connected to the control input of the discriminator circuit, for controlling the discriminator circuit so as to transfer a next signal level to the respective register circuit without discrimination.
Thus, it is achieved that in the case of a temporary absence of lower and/or higher signal levels, such as in the case of flaws or fingermarks on an information carrier being read, the arrangement ensures that the correct discrimination level and the correct slicer level are re-centered with respect to higher incoming signal levels and lower incoming signal levels. The gist of it is that if one of the two signal levels has not or both signal levels have not appeared after a first time interval the discriminator circuit yet supplies a signal, in which case it does not make any difference for the operation of the arrangement whether the incoming signal level thus supplied is a low or a high incoming signal level and is supplied to the register circuit for high or low incoming signal levels, respectively. The discriminator circuit in fact no longer discriminates.
Particularly the arrangement in which each of the register circuits performs an operation upon applied incoming signal levels, which operation is defined in that a new register mean value is determined by multiplying the current register mean value by a factor (1xe2x88x92xcex1), where 0 less than xcex1 less than 1, and adding thereto a new incoming signal level to be added, which level has been multiplied by a factor xcex1, makes it possible to discriminate between scratches and fingermarks on the information carrier with the aid of the timing circuit. By a suitable choice of the factor xcex1 and the duration of the predetermined time interval it is possible to maintain the register mean value and, consequently, the discrimination level and the slicer level during a scratch of short duration, while during a fingermark, which is generally of a longer duration than a scratch, the arrangement will search for the correct discrimination level and the slicer level after expiry of the predetermined time interval. A further advantage of this embodiment is that during the search for the correct level after expiry of the predetermined time interval xe2x80x9cdetectedxe2x80x9d bits may be marked as xe2x80x9cnot presentxe2x80x9d for the purpose of error corrections.